A Compact Charge-Based 4-Bit Flash ADC Circuit Architecture for ANN Applications

A charge-based flash analog digital converter (ADC) circuit architecture is presented, which can be used in various artificial neural network (ANN) applications where compactness and high conversion speed are critical. The 4-bit $'& KDV EHHQ UHDOL]HG ZLWK P GRXEOH SRO\ SURFHVV DQG tested, confirming its linearity over the full range and a conversion speed of 10 Msamples / s. Introduction : The requirements of A/D conversion in mixed analog-digital ANN architectures may impose unique specifications on ADC circuit performance which are quite different from classical ADC performance requirements. The silicon area occupied by the ADC should be minimized, since a large number of such units are typically needed in ANN architectures. The sampling speed should be as high as possible, in order to accommodate fast-changing input signals such as those encountered in real-time image processing and pattern recognition. The required accuracy (resolution), on the other hand, may be lower than that used in most of classical ADC applications, since the inherently error-tolerant properties of ANN operation typically compensates for the lower resolution of the processed signal. Here, we present a very compact flash ADC circuit architecture which is based on the charge-based Capacitive Threshold Logic (CTL) circuit concept introduced earlier [1]. The circuit is CMOS-compatible, operates on a simple twophase non-overlapping clock scheme, and it requires no externally generated reference voltage levels other than VDD and GND for its operation. Circuit description : The circuit diagram of a 4-bit CTLbased ADC is given in Fig. 1. The converter essentially consists of four threshold logic gates, i.e., four capacitive rows, which accommodate analog and digital input signals. The capacitive threshold logic gates are actually connected in a cascade configuration; the gate that generates the most significant bit (MSB) output is directly driven by the analog input signal, whereas the gates that generate the lesser significant bits are driven by the analog input as well as by the higher-order digital output signals. At the functional level, the operation of the four CTL gates can be described as follows: VOUT3 = VDD if VA > (8/16) VDD (1) VOUT2 = VDD if VA > (12/16) VDD – (8/16) OUT3 V VOUT1 = VDD if VA > (14/16) VDD – (8/16) OUT3 V – (4/16) OUT2 V VOUT0 = VDD if VA > (15/16) VDD – (8/16) OUT3 V – (4/16) OUT2 V – (2/16) OUT1 V Note that the four output bits (VOUT0 through VOUT3) are generated by four “threshold decisions”, each of which is performed by a mixed-input CTL gate. The inherently recursive nature of the decision process described in (1) implies that the LSB-delay is proportional to the number of bits in the output word, and that the higher-order outputs create a ripple effect for the lower-order bits. Yet, the entire conversion operation given in (1) can be completed in a single clock cycle. As opposed to earlier, similar charge-based ADC architectures [2], [3], this circuit does not require a subsequent decoder circuitry to convert a “thermometer code” output of voltage comparators into conventional binary output.